Publications

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Autonoma de Barcelona (UAB), Bellaterra, Spain, Embedded Real Time Systems (ERST) 2024 conference

RISC-V on mixed-critical platforms (poster + published extended abstract), Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya and George Violettas, RISC-V Summit Munich 2024

SETHET – Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story, Gabriele Magnani1, Daniele Cattaneo1, Lev Denisov1, Giuseppe Tagliavini2, Giovanni Agosta1, Stefano Cherubin3 1 Politecnico di Milano (Italy), 2 University of Bologna (Italy), 3 NTNU (Norway), ACM Computing Frontiers 2024

Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching, Matthias Rupp, Stefan Wallentowitz, ARCS Conference 2024

MX: Enhancing RISC-V’s Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication, Matteo Perotti†, Yichao Zhang†, Matheus Cavalcante†, Enis Mustafa†, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), DATE 2024 Conference, https://arxiv.org/pdf/2401.04012.pdf

An MDA based Approach for Target Language Independent Sequential Code Generation, Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, MBMV 2024

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems, Natalie Simson, Ares Tahiraga and Wolfgang Ecker, MBMV 2024

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, https://upcommons.upc.edu/bitstream/handle/2117/397442/SafeTI_DFTSCongre...

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core, Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella, IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, https://upcommons.upc.edu/bitstream/2117/393235/1/safels_camera_ready.pdf

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project, William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario DiCarlo, and Antonio Sciarappa, 1 Politecnico di Milano, Milano, Italy, 2 University of Bologna, Bologna, Italy, 3 E4 Computer Engineering SpA, Italy, 4 Thales Alenia Space Italia S.p.A., Italy, 5 Politecnico di Torino, Torino, Italy, 6 Leonardo SpA, Italy, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2023 conference, https://re.public.polimi.it/retrieve/ceb20d00-33d1-41df-8a37-1870b06ea92...