Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads, Matteo Perotti†, Michele Raeber†, Mattia Sinigaglia*, Matheus Cavalcante†, Davide Rossi*, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), ASAP 2024 Conference, https://arxiv.org/abs/2407.05447

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain, Embedded Real Time Systems (ERST) 2024 conference, https://hal.science/hal-04614786

RISC-V on mixed-critical platforms (poster + published extended abstract), Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya and George Violettas, RISC-V Summit Munich 2024,

SETHET – Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story, Gabriele Magnani1, Daniele Cattaneo1, Lev Denisov1, Giuseppe Tagliavini2, Giovanni Agosta1, Stefano Cherubin3; 1 Politecnico di Milano (Italy), 2 University of Bologna (Italy), 3 NTNU (Norway), ACM Computing Frontiers 2024,

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine, Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomas Gomez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini, IEEE Journal of Solid-State Circuits, https://hdl.handle.net/11585/953203

Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching, Matthias Rupp, Stefan Wallentowitz, ARCS Conference 2024,

The European Chips Act, The ISOLDE Project, and Open-Source Hardware, Willibald Krenn; Andrew Wilson; Ambily Suresh; Manuel Freiberger (Silicon Austria Labs, Graz), 2024 Argentine Conference on Electronics (CAE),

MX: Enhancing RISC-V’s Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication, Matteo Perotti†, Yichao Zhang†, Matheus Cavalcante†, Enis Mustafa†, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), DATE 2024 Conference, https://arxiv.org/pdf/2401.04012.pdf

A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation, Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564525

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems, Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564506

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, http://hdl.handle.net/2117/397442

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core, Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella, IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, http://hdl.handle.net/2117/393235

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project, William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario DiCarlo, and Antonio Sciarappa, 1 Politecnico di Milano, Milano, Italy, 2 University of Bologna, Bologna, Italy, 3 E4 Computer Engineering SpA, Italy, 4 Thales Alenia Space Italia S.p.A., Italy, 5 Politecnico di Torino, Torino, Italy, 6 Leonardo SpA, Italy, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2023 conference, https://re.public.polimi.it/retrieve/ceb20d00-33d1-41df-8a37-1870b06ea92...

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains, Jaume Abella, Francisco J. Cazorla, Sergi Alcaide, Michael Paulitsch, Yang Peng, Inês Pinto Gouveia, (white paper), https://arxiv.org/abs/2307.11940

ISOLDE review in Brussels

Last week, the ISOLDE consortium completed its 18-month review to share the latest advancements of the project with the European Commission. The collaboration of all participants provided valuable insights making the session a place for showing the progress of the project and sharing feedback.

This meeting represented a significant milestone for the ISOLDE project, aimed at developing advanced RISC-V processing systems to enhance European industries. Accomplishing this objective holds the potential to revolutionize key sectors in Europe, including automotive, aerospace, and IoT.

During three full days, ISOLDE’s partners dedicated their effort to analyse every element of their work, leaving no doubt about each point of the tasks they needed to discuss and strategizing the path forward.

The attendees at the meeting ranged from our Work Package leaders to some Task leaders and members from all 35 partner organizations, who brought their points of view both in-person in Brussels and remotely.

Moreover, presentations showcased at the event received positive feedback, confirming the dedication of all those involved in the project.

Following the review, the ISOLDE consortium gathered for an after-work social event, providing a welcome opportunity for participants to establish personal connections outside of the professional environment.

The ISOLDE project is growing stronger than ever as its partners continue to attain its goals together. Stay tuned to ISOLDE’s news through our website and social media channels and be aware of all our upcoming milestones!

ISOLDE and RISC-V Summit Europe

One of the goals of ISOLDE is to strengthen the dissemination of RISC-V projects in Europe, and ISOLDE partner HM has taken a lead role here with the local organization of RISC-V Summit Europe 2024. It will be held in Munich from June 24 to June 28. As a literal “summit” it will bring together the entire community in Europe, including industry, academia and individual developers.

After the pandemic, there are now three RISC-V Summits around the globe, focusing on the key markets of RISC-V: RISC-V Summit North America, RISC-V Summit Europe and RISC-V Summit China. RISC-V Summit Europe is the joint effort of three key communities from France, Germany and Spain, together with RISC-V International. The steering and program committees include the variety of the European community. Compared to the other summits, Europe traditionally had a more research centric approach, which still reflects on the strong academic impact of the European ecosystem in this community. With over 180 submissions, the RISC-V Summit Europe is the place to present.

But with the rapid adoption of RISC-V in Europe, driven by that strong research ecosystem, we can see an increasing interest and participation from industry. At this year's RISC-V Summit Europe, for example, the CTO of Thales, Bernhard Quendt, will hold a keynote, accompanied by the SVP of Automotive Microcontrollers at Infineon, Thomas Böhm. The key person behind RISC-V, Krste Asanović, will present the State-of-the-Union of RISC-V. Other invited presenters include Alex Kocher, CEO of the Joint Venture Quintauris, and Johanna Bähr, Research Associate at Fraunhofer. Larry Wikelius, Director of the RISC-V Software Ecosystem (RISE) organization will give an update. And last but not least, the first batch of invited speakers includes Edward Wilford of Omdia, who as a Senior Principal Analyst will be speaking about RISC-V adoption in the microcontroller market and beyond.

The program will start on Monday with Technical Workgroup Meetings. The main program and expo will run from Tuesday to Thursday. Friday will be available for RISC-V focused projects to meet or disseminate their work. As RISC-V Summit Europe is the denoted “main summit” this year, the annual general meeting of all RISC-V members and an award ceremony will be part of the program.

About the HM:

Hochschule München (HM) is one of the largest universities of applied sciences in Germany. Their technical involvement in ISOLDE focuses on open-source CPU support for bytecode virtualization and an improved fault injection framework around the open-source tool Verilator. Beyond the technical contributions, HM is strongly involved in dissemination events. With HM professor Stefan Wallentowitz on the RISC-V board of directors, an impactful advocate of RISC-V is active in the ISOLDE project.

Generating Resilient System-on-a-Chip Architectures for RISC-V

The overarching aim of ISOLDE is to provide a high-performance RISC-V based system-on-a-chip (SoC) with a level of functionality, safety, security and power efficiency that is competitive with existing commercial/proprietary alternatives.

At the FZI, we support this vision with an approach to integrate safety patterns for hardware using a model-driven design approach. The foundation builds the Rocket Chip Generator framework maintained by the Chips Alliance. Using a model-driven approach, the architecture of the hardware design is abstracted and transformations on this abstract model integrate different architectural safety patterns, such as Triple Modular Redundancy (TMR). By feeding back the modified model into the generator approach, the hardened architecture can be generated and afterward synthesized.

For the model-driven approach, we build upon the Universal Safety Format (USF), which was primarily designed for hardening software architectures. Within ISOLDE, we would like to adopt this format and the underlying principles for hardware designs. By choosing an approach originating form software, we anticipate creating a design flow that can address both the hardware as well as the corresponding software part that is often required when introducing hardware safety features, such as a watchdog timer.

This automated integration approach is supported by an early system-level/RTL co-simulation approach. We utilize the design artifacts of the Rocket Chip Generator, such as the RTL description of the peripherals as well as the device tree of the SoC, to generate simulation models and configure a QEMU core simulation. With such a simulation, it is possible to evaluate the hardware/software system, especially the effectiveness of the integrated safety mechanism.

The two approaches enable a rapid exploration of different safety architectures in the generative SoC design flow.

About the FZI:

As an independent foundation, the FZI Research Center for Information Technology has stood for applied cutting-edge research in the field of computer science and its application fields for over 35 years. The FZI researches and develops innovations for the benefit of society and offers excellent researchers a unique springboard to their professional future. For its partners from industry, business, science, associations, and the public sector, the FZI serves as an institution research, training and transfer.

Research teams at the FZI interdisciplinarily develop and prototype concepts, software, hardware and system solutions for their clients. Scientific excellence and interdisciplinary practice are therefore well established at the FZI.


Leveraging RISC-V systems’ safety by using hypervisors

The ISOLDE project aims to develop a high performance RISC-V ecosystem to be able to compete with the existing alternatives of the market. For achieving this, advanced architectures, accelerators and IPs will be implemented together with a full SW stack which allows its use in a wide spectrum of applications. The different components that will be developed within the project will be integrated in major designs to be used in different applications sectors, such as automotive or space ones, which corresponds to safety-critical domains.

In those safety-critical domains the use of hypervisors, such as the XtratuM Next Generation (XNG) hypervisor developed by FENTISS, is widely extended as it enhances the safety of the systems by providing temporal and spatial isolation of safety mixed-critical applications. The XNG hypervisor is a Type I hypervisor qualified for space (ECSS level B) over different types of processors. It is inspired in well accepted standards such as ARINC 653, employed by highly criticality software, and allows running partitions based on a minimal runtime (XtratuM Runtime Environment or XRE), Real Time Operating Systems such as RTEMS, used by a majority of space missions, or General Purpose Operating Systems such as Linux.

As part of the work to be carried out in ISOLDE, FENTISS will adapt the XNG hypervisor to support the new RISC-V standards, as well as to integrate the developed safety and security related technology. FENTISS will adapt the XNG hypervisor to the CVA-6 processor core, and in addition support the new features introduced in the NOEL-V core. Moreover, FENTISS will collaborate on the project with different partners such as UPV and RAPITA, working together to integrate in XNG different validation tools developed by these partners. FENTISS will also collaborate inside the scope of the project with BSC, by supporting in the XNG hypervisor some safety-related IP cores such as the SafeSU and the SafeTI, developed by this organization.

Open-source vector units for RISC-V

The Digital Circuits and Systems Group of ETH Zürich has been working on open-source hardware since 2013 under the PULP platform banner (https://pulp-platform.org/). As a founding member of the RISC-V foundation, ETH Zürich has designed some of the most commonly used RISC-V processor cores, such as CVA6/Ariane, CV32E40P/RI5CY, and Ibex/ZeroRiscy. ETH Zürich also has significant experience in ASIC design, having implemented over 50 ASICs manufactured using PULP-based open-source HW (http://asic.ethz.ch/). ETH Zürich is excited to bring this experience to the ISOLDE project and work with partners on establishing high-performance RISC-V-based computing systems that can be used in industrial quality products.

Our world has an endless appetite for additional computing power that triggers the digital revolution. At the same time, the raw electrical power needed for computing has reached levels that can not sustain this growth rate anymore. Simply put, the world needs more efficient ways of performing computing, doing more of it while spending less energy to do so.

Classical (von Neumann) computers have not changed much since their inception, and in very simplified terms, computer programs fetch simple instructions from memory that tell them what to do and then go fetch operands from memory, perform the operation, and then copy the result back to memory.

One of the ways to improve the efficiency of computing is to reduce the effort to perform this part of the operation. In regular (scalar) processing, the instruction tells the processor what to do with one word of data (usually 64 bits). So, if an array of data is being processed (with, for example, 1000 elements), the processor repeats the same task for all the elements in the array. Vector processing tries to take advantage of this and specifies operations on large vectors. A simple vector instruction can be used to schedule 1000 additions instead of executing 1000 individual additions separately. As long as you have many such operations, you can perform them more efficiently.

To this extent, the RISC-V ISA defines the RISC-V Vector extension (RVV), a set of instructions to perform vector operations (https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), and ETH Zürich has been investigating different approaches on how to a) implement such vector engines and b) pair them with existing processors to extend their capabilities.

The Ara design started when the RVV specification was still in its early stages and has been designed to work in tandem with the CVA6/Ariane core. Versions of this openly available core have already been taped out, as can be seen in Figure 1.

Figure 1 - Die shot of the Yun chip. Highlighted: CVA6, the scalar processor with its level-1 cache memories, and Ara’s four vector lanes with their Vector Register File (VRF) chunks. In the upper-right corner: peripherals and main level-2 scratchpad (SP) memory.

Ara was designed to efficiently accelerate the computation of long vectors and showed the potential of RVV by reaching almost peak performance on ubiquitous kernels such as matrix multiplications and convolutions, which are largely used in machine learning tasks. Figure 2 shows the power breakdown of combined CVA6/Ara executing a large matrix multiplication that can take advantage of the vector extensions.

Figure 2 - Ara Power consumption breakdown during a matrix multiplication. Most of the power is spent in the vector floating-point unit (VMFPU), which is where the core computation is done. The vector architecture helps keep the power related to the fetch of the instruction low, as testified by the small 2.4% of the budget taken by CVA6’s instruction cache.

A second approach the group has taken is to explore how the vector processor architecture maps to the embedded world by developing a tiny and efficient integer-only 32-bit vector accelerator named Spatz (Figure 3) that can be integrated into the Mempool many-core system. Spatz, as opposed to Ara, was coupled with a tiny and agile scalar processor called Snitch and further showed the potential of RVV in a more constrained processing domain.

Since the first Ara prototype, ETH Zurich has explored different ways of coupling vector accelerators to scalar processors, and many different interfaces were changed over time, with a particular interest toward the OpenHW Group’s X-interface, already used with an early design of Spatz. Currently, the open-source Ara is being actively developed following the last development of the specifications.

Figure 3 - Spatz architecture. Spatz works in tandem with the Snitch processor by means of the X-interface.

As mentioned before, processors usually operate at a fixed size of words (usually 64-bit), which means that any value that is computed is represented by 8 bytes in memory. There are some applications where the range of numbers that are used in computing is quite limited (for example, 0-100), and the same amount of memory can be used to represent multiple different numbers, significantly reducing the memory needs and the computation complexity, with a reduction of the overall energy needed to perform these operations.

To be effective and efficient, a computing system needs to handle different types of number representations. These multi-precision computing blocks allow computing to take place in the most efficient number representation while allowing the full range of capabilities to remain intact.

ETH Zürich has been actively working on exploring efficient arithmetic computing units that can support multiple number formats, mainly through the fpnew, a RISC-V-compliant Floating-Point Unit (FPU) originally developed with multi-precision capabilities as one of its fundamental goals and now maintained by OpenHW Group under the name cvfpu. Its modular multi-precision-ready design allows for computing floating-point operations from 64-bit to 8-bit floating-point data. It also supports alternative formats for 16 and 8 bits, more and more used in the machine learning domain.

Vector processing and multi-precision capabilities are fundamental steps toward fast and efficient processing in an era in which focusing the power where it is really needed, without any waste, is paramount. To this extent, ETH Zurich is working on fully supporting the cvfpu multi-precision capabilities on the Ara vector processor to unleash even higher energy efficiency during the computation.

In ISOLDE, we aim to apply this know-how to multi-precision Vector processing units paired with RISC-V cores to improve the efficiency of the target use cases and provide Europe and the whole open-source community at large with new tools to tackle the upcoming computational challenges.

The ISOLDE Space Demonstrator: Embracing RISC-V for Space Applications

The ISOLDE project is dedicated to advancing the development of high-performance RISC-V processing systems, with the goal of empowering European industries and fostering digital sovereignty of the EU. By the completion of the project, ISOLDE aims to have systems and platforms that will be demonstrated in major European application areas, including automotive, space, and IoT. Moreover, it is expected that two years after completion, the high-performance components developed by ISOLDE will be integrated into industrial-quality products. Among the demonstrators envisioned in the project, E4 Computer Engineering will focus on developing a demonstrator in the space sector.

The Space Demonstrator is one of the key components of the project, which involves constructing a FPGA and a ready-to-tapeout multicore SoC design specifically designed for space applications. The Space Demonstrator will be used to validate the feasibility and performance of RISC-V-based SoCs in space environments. This will pave the way for wider adoption of RISC-V in future space missions. The integration of a RISC-V processor into the Space Demonstrator represents a pivotal advancement in spacecraft capabilities. RISC-V's open-source architecture brings several advantages to space applications, including reduced costs due to the absence of licensing fees and adaptability to meet specific space requirements.

E4 plays a crucial role in the development of the space demonstrator, ranging from a preliminary definition of the requirements for the demonstrator and extending to the implementation of the FPGA and the development of test methodologies to validate correctness and functionality of the implementation. E4 will also facilitate the synchronization of software design with the implementation and testing of the demonstrator and, additionally, will collaborate on the development of V&V methodologies and APIs. Our involvement spans the entire design of this demonstrator, from its inception to its completion, with the goal of creating a high-performance, reliable, and secure demonstrator that illustrates RISC-V processing systems for space applications.

As the ISOLDE project progresses, the Space Demonstrator will serve as a platform to validate the feasibility and performance of RISC-V-based SoCs in space environments. This validation process will contribute to the broader adoption of RISC-V in future, fostering the development of a robust European RISC-V ecosystem.

How RISC-V may contribute to the energy transition with Consolinno Energy GmbH

According to the European Union's energy and climate targets, greenhouse gas emissions are to be reduced to zero by 2050. The Paris Climate Agreement calls for global warming to be limited to 1.5 degrees Celsius. Achieving these targets requires a switch to renewable energies such as wind power and photovoltaics. This requires a reform of the energy industry, which poses technological challenges for European countries.

In terms of dimensioning and control, the current electricity grid is designed for a small number of centralised, controllable power plants on the one hand and static consumers on the other. However, the proportion of decentralised, emission-free energy generation plants is constantly increasing. Many of these systems do not supply their energy constantly, but with large fluctuations throughout the day. Cushioning such fluctuations completely with batteries is not realistic, as this would require gigantic storage capacities. At the same time, single and multi-family homes, which represent a large proportion of energy consumers, can no longer be modelled using static load profiles alone. Interconnected, controllable devices such as heat pumps, battery storage systems and smart household appliances are becoming increasingly widespread in residential properties, offering flexibility in consumption. With the strong growth of electromobility, the electric car is another flexible consumer that can be used temporarily as a buffer storage or energy supplier. It is therefore important to use this flexibility and adapt the consumers to the fluctuating generation in the best possible way through energy optimisation.

Making a contribution to meeting the Paris climate targets through energy efficiency has been the goal of Consolinno Energy GmbH since it was founded in 2017. The young GreenTech company from Regensburg, Germany, realises efficient energy solutions with innovative technologies (AI, IoT, Cloud, Edge) and smart energy planning. Consolinno relies on hardware systems developed in-house, customised software and storage and visualisation in the cloud. AI plays a decisive role here with schedule management. When used in neighbourhoods, sector coupling takes place: components such as combined heat and power plant (CHP), photovoltaic (PV) and battery are interconnected and automated for the best possible energy efficiency. The solutions are part of smart home automation as well: the devices therefore also regulate the energy flow in single-family homes. Consolinno has developed the manufacturer-independent energy manager Leaflet HEMS (home energy management system) for this purpose. The Leaflet HEMS is also equipped for future topics such as grid serviceability and dynamic tariffs.

Credits: Consolinno Energy

The ISOLDE research project is focussing on the further development of the RISC-V instruction set architecture (ISA). This ISA could represent serious competition for the dominant ARM and x86 architectures in the future and has the special characteristics of being modular and open source. This means that with RISC-V, any company can in principle purchase its own customised microprocessor unit (MPU) or even develop one itself. Many partners in ISOLDE take care of the design or improvement of the RISC-V architecture or associated extensions. Consolinno Energy GmbH is taking part in the project in the role of the user and is investigating whether a RISC-V processor could be used to develop a real, competitive IoT product in the energy sector.

As part of the ISOLDE project, Consolinno therefore wants to investigate the feasibility of a completely open-source energy management system based on RISC-V, embedded Linux and OpenEMS. The aim is also to investigate whether it is possible to transfer an existing ARM-based software stack to a RISC-V processor. In addition, Consolinno wants to explore the possibilites of optimisation of energy systems on the edge in greater depth and, if possible, make use of hardware accelerators on the RISC-V platform. The aim is to show that RISC-V is not just a playground for science and research, but may also be used as a reliable building block for companies in the private sector.


Consolinno Energy GmbH: https://consolinno.de

OpenEMS: https://openems.io

Towards a green and digitally autonomous Europe with the ISOLDE project


Are you familiar with the medieval love story about Tristan and Isolde? Well, this is not it. We are talking about ISOLDE as in HIgh Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems. This project kicked off in early 2023 and engages more than 40 partners from 9 different European countries. ISOLDE aims to support Europe’s digital transformation within various sectors to speed up the transition towards a green and digitally autonomous Europe. Central to this ambition is the goal of strengthening the design capacity across the EU.

Innovation for sustainability

To achieve these ambitious goals, the members of the project will create high-performance, industrial-grade processing systems and platforms based on RISC-V. Codasip’s role is to customize our existing RISC-V cores for a selected set of compute-intensive automotive applications. Firstly, we are working closely with other partners in the project to define the requirements for the tailoring of the computing architecture. Next, we will focus on application analysis and processor customization. We will of course also do extensive work on benchmarking, parametrization, and verification.
So how do we customize a processor to make it more efficient? One very effective way is to add custom instructions. But there is more to it. In addition, you can use techniques such as increasing the data throughput, parallelizing operations, or managing specific data types. Also, you can add application-related features. At Codasip, we call this Custom Compute.

Custom Compute enables innovation for sustainability. You can learn more in our recent blog post on saving the planet, one byte at a time.

How to design products differently to reduce the carbon footprint, here using a mobile phone as an example

RISC-V commercialization

A key pillar of Codasip Labs is the commercialization of innovation. This is a perfect match with the aims of the ISOLDE project.

Technology readiness level (TRL) is a method for estimating the maturity of a technology. TRLs were first introduced by NASA and have been adopted, and adapted, by the European Commission. The commission has defined the following 9 TRLs:


basic principles observed


technology concept formulated


experimental proof of concept


technology validated in lab


technology validated in relevant environment 

(industrially relevant environment in the case of key enabling technologies)


technology demonstrated in relevant environment 

(industrially relevant environment in the case of key enabling technologies)


system prototype demonstration in operational environment


system complete and qualified


actual system proven in operational environment 

(competitive manufacturing in the case of key enabling technologies; or in space)

Extract from Part 19 - Commission Decision C(2014)4995

Why am I telling you about TRLs? Well, because the ISOLDE project intends to provide RISC-V-based platforms at least at TRL 7. This means that at the end of the project in 2026, the participants will not only have created proof of concepts. Rather, we will actually have validated and demonstrated the solutions in an operational environment. This means that the project will deliver solutions that can be
used in industrial quality products. The outcome is expected to be part of actual systems within a couple of years from the project’s end date. Key application domains for the technology include automotive, space, and IoT. Surely with this ambitious aim, ISOLDE will further accelerate RISC-V commercialization.

A green and digitally autonomous Europe

An interesting aspect of ISOLDE is the included requirements to support European digital sovereignty. All participating partners are in Europe. In the end, the resulting customizable IP cores will be hosted on European servers. The more than 40 involved organizations represent large parts of EU critical chip infrastructure. This ecosystem is currently establishing the requirements and specifications for the building blocks that the project will develop.

By the time the project comes to an end, ISOLDE will have delivered a major contribution to the RISC-V ecosystem. Particularly, the project will benefit embedded high-performance computing, and contribute to the design capacity across the European chip industry.


Note: The project “ISOLDE” has received funding from the European Union HE Research and Innovation programme under grant agreement No 101112274. Codasip s.r.o, as a Czech participant in this project, is supported by the Ministry of Education, Youth and Sports.

First ISOLDE’s progress meeting in Valencia

Last week, the ISOLDE consortium met in Valencia in their first progress meeting after the kick-off to share the latest updates of the project. The Polytechnic University of Valencia was the perfect location for this event which hosted more than 50 attendees of the different organizations that take part in this distinguished Horizon Europe project.

This meeting marked significant strides towards ISOLDE’s goal of developing high-performance RISC-V processing systems and platforms which will revolutionize key European application domains such as automotive, space, and IoT.

During two days of full activity, the ISOLDE team converged to discuss and strategize the path forward. With experts from diverse organizations and markets, discussions were enriched by a multitude of perspectives, fostering a collaborative spirit essential to the success of the project.

This first progress meeting served as a platform to unveil the progress achieved in the past months for the development of high-performance RISC-V processing systems and platforms. Task leaders showcased the advancements of each work package and the future activities that will be performed in the next months. Attendees participated in meaningful discussions to find all possible ways of collaboration and achieve the best result.

With a focus on key European application domains, including automotive, space, and IoT, ISOLDE will deliver high performance components also partly to the open-source community which will be used in industrial quality products. The excellent work carried out and the cooperation between partners during the meeting shows ISOLDE’s commitment to addressing real-world challenges and propelling Europe to the forefront of technological innovation.

Now, it is time to continue working together and drive positive impact across industries. As the project progresses, stay connected with ISOLDE through our website and social media channels!