ISOLDE

ISOLDE's open access publications are available at https://zenodo.org/communities/isolde.

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites, Emanuele Valpreda, Roberto Morelli, Antonio Sciarappa, Davide Di Ienno, Carlo Ciancarelli, Paolo Serri, Valeria Parascandolo, antonio leboffe, Dario Pascucci, Daniele Gregori, Mattia Paladino, Daniele Jahier Pagliari, Alessio Burrello, Sara Vinco, Gianvito Urgese, Maurizio Martina, Guido Masera, William Fornaciari, Federico Reghenzani, Andrea Galimberti, Giovanni Agosta, Davide Zoni, Andrea Acquaviva, Francesco Conti, RISC-V in Space Workshop,

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs, Pablo Andreu, Sergi Alcaide, Pedro Lopez, Jaume Abella, Carles Hernández, Future Generation Computer Systems, https://www.sciencedirect.com/science/article/pii/S0167739X24004825

Model Predictive Control Acceleration on RISC-V, Martin Kostal, NXP Semiconductors, Poster, HiPeac 2025, https://doi.org/10.5281/zenodo.15556756

SIMD Extensions – A Historical Perspective, Diana Vuta-Popescu, Ionut, Catalin Antofi, Catalin Bogdan Ciobanu, Csaba Zoltan Kertesz, 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME),

TIE Micro – Chiplets and Next-gen Packaging, Catalin Bogdan Ciobanu, Dan Manolescu, Roxana Vladuta, Luciana Chitu, Cosmin Moisa, Marcel Manofu, Paul Svasta, 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME),

Systolic Array Matrix Multiplication Accelerator, Alexandru Puscasu, Catalin Bogdan Ciobanu, Octavian Buiu, International Semiconductor Conference (CAS),

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads, Matteo Perotti†, Michele Raeber†, Mattia Sinigaglia*, Matheus Cavalcante†, Davide Rossi*, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), ASAP 2024 Conference, https://arxiv.org/abs/2407.05447

RISC-V Accelerators, Enablement and Applications for Automotive and Smart Home in the ISOLDE Project, Cătălin Bogdan Ciobanu, Honorius Gâlmeanu, Alexandru Puscasu, Mihai Gologanu, Octavian Buiu, Mihai Antonescu, Vlad-Gabriel Serbu, Vasile-Mădălin Moise, Cristian-Tiberius Axinte, Alexandru-Tudor Popovici, George-Iulian Uleru, Andrei Stan, Mihai Munteanu, Alexandru Drîmbărean, Csaba Nemeti, Dănut Rotar, Cosmin Moisa, Bogdan Ditu, Petre Cristian Trusca, Marius Antache, Simona Costinescu, Mari-Anais Sachian, George Suciu, Cristian Gheorghe, Cristina Tudor, Kejsi Koci, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2024 conference,

Integration and Optimization of EV Charging Processes in a Decentralized Local Energy Trading Market, Christoph Groß; Tin Stribor Sohn; Oliver Bringmann, 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS), https://www.researchgate.net/publication/383162902_Integration_and_Optim...

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain, Embedded Real Time Systems (ERTS) 2024 conference, https://hal.science/hal-04614786

RISC-V on mixed-critical platforms (poster + published extended abstract), Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya and George Violettas, RISC-V Summit Munich 2024, https://www.sysgo.com/fileadmin/user_upload/data/blog/SYSGO_2024-06_Mixe...

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium, Xavier Carril, Charalampos Kardaris, Jordi Ribes-González, Oriol Farràs, Carles Hernandez, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó, ACM Transactions on Reconfigurable Technology and Systems, https://dl.acm.org/doi/abs/10.1145/3675172

SETHET – Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story, Gabriele Magnani1, Daniele Cattaneo1, Lev Denisov1, Giuseppe Tagliavini2, Giovanni Agosta1, Stefano Cherubin3; 1 Politecnico di Milano (Italy), 2 University of Bologna (Italy), 3 NTNU (Norway), ACM Computing Frontiers 2024,

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine, Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomas Gomez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini, IEEE Journal of Solid-State Circuits, https://hdl.handle.net/11585/953203

Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching, Matthias Rupp, Stefan Wallentowitz, ARCS Conference 2024, https://zenodo.org/records/15471894

The European Chips Act, The ISOLDE Project, and Open-Source Hardware, Willibald Krenn; Andrew Wilson; Ambily Suresh; Manuel Freiberger (Silicon Austria Labs, Graz), 2024 Argentine Conference on Electronics (CAE), https://zenodo.org/records/15479371

MX: Enhancing RISC-V’s Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication, Matteo Perotti†, Yichao Zhang†, Matheus Cavalcante†, Enis Mustafa†, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), DATE 2024 Conference, https://arxiv.org/pdf/2401.04012.pdf

A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation, Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564525

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems, Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564506

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, http://hdl.handle.net/2117/397442

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core, Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella, IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, http://hdl.handle.net/2117/393235

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project, William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario DiCarlo, and Antonio Sciarappa, 1 Politecnico di Milano, Milano, Italy, 2 University of Bologna, Bologna, Italy, 3 E4 Computer Engineering SpA, Italy, 4 Thales Alenia Space Italia S.p.A., Italy, 5 Politecnico di Torino, Torino, Italy, 6 Leonardo SpA, Italy, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2023 conference, https://re.public.polimi.it/retrieve/ceb20d00-33d1-41df-8a37-1870b06ea92...

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains, Jaume Abella, Francisco J. Cazorla, Sergi Alcaide, Michael Paulitsch, Yang Peng, Inês Pinto Gouveia, (white paper), https://arxiv.org/abs/2307.11940

Synergistic memory optimisations: precision tuning in heterogeneous memory hierarchies, Gabriele Magnani 1, Daniele Cattaneo 1, Lev Denisov 1, Giuseppe Tagliavini 1, Giovanni Agosta 1, Stefano Cherubin 1, G. Magnani 1, D. Cattaneo 1, L. Denisov 1, G. Tagliavini 2, G. Agosta 1 and S. Cherubin 3; 1 DEIB, Politecnico di Milano, Milan, Italy; 2 DISI, University of Bologna, Bologna, Italy; 3 IDI, NTNU, Trondheim, Norway., IEEE TRANSACTIONS ON COMPUTERS, VOL. XX, NO. X, AUGUST 202X,

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors, Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini, DATE 2025 Conference, https://arxiv.org/abs/2501.10301

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution, Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini, Computing Frontiers 2025, https://www.arxiv.org/abs/2505.24363

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor, Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Computing Frontiers 2025, https://arxiv.org/abs/2504.05718

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance, Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini, OSHW (Computing Frontiers 2025), https://arxiv.org/abs/2504.10345

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency, Matteo Perotti, Samuel Riedel, Matheus Cavalcante, Luca Benini, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, https://arxiv.org/abs/2309.10137

Benchmarking WebAssembly for Embedded Systems, Konrad Moron, Stefan Wallentowitz, ACM Transactions on Architecture and Compiler Optimizations, https://dl.acm.org/doi/10.1145/3736169

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices, Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, and Daniele Jahier Pagliari., Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions, https://arxiv.org/abs/2404.01861

Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform, Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini, IEEE Transactions on Circuits and Systems for Artificial Intelligence, https://arxiv.org/abs/2405.19284

Joint Pruning and Channel-Wise Mixed-Precision Quantization for Efficient Deep Neural Networks, Beatrice Alessandra Motetti, Matteo Risso, Alessio Burrello, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari, IEEE Transactions on Computers, https://arxiv.org/abs/2407.01054

MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices, Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda, Josse Van Delm, Arne Symons, Luca Benini, Marian Verhelst, Daniele Jahier Pagliari, Alessio Burrello, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, https://arxiv.org/abs/2410.08855

A Hardware Accelerator for Secure Communications through Post Quantum Cryptography, Ambily Suresh, Andrew Wilson, Diego Gigena-Ivanovich, Manuel Freiberger, and Willibald Krenn, RISC-V in Space Workshop 2025, https://zenodo.org/records/15480570

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure, Sven Mehlhop, Jörg Walter, Frank Oppenheimer, Forum on specification & Design Languages, https://zenodo.org/records/16418944

Modern LLVM-based Compiler Autotuning for WCET Optimization, Gabriele Magnani, Davide Baroffio, Federico Reghenzani, Giovanni Agosta, William Fornaciari, IEEE Real-Time Systems Symposium,

Low Complexity Safety Concept for Field-Oriented Control of Permanent Magnet Synchronous Motor, Pavel Svadbik, Martin Sumega, Milan Brejl, 2025 the 9th International Conference on System Reliability and Safety,

HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCs, Luigi Ghionda, Riccardo Tedeschi, Yvan Tortorella, Arpan Suravi Prasad, Davide Rossi, Luca Benini, Francesco Conti, 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Kalamata, Greece, 2025,

A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU, Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti, IEEE Journal on Emerging and Selected Topics in Circuits and Systems,

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications, Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gurkaynak, Davide Rossi, Luca Benini, IEEE Transactions on Circuits and Systems I: Regular Papers,

TRISTAN & ISOLDE Chips-JU RISC-V Projects, Cătălin Bogdan Ciobanu, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Dominik Baumann, Alexandru Pușcașu, Mihai Gologanu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, Jörg Walter, Gianvito Urgese, Michelangelo Barocci, Tommaso Terzano, Guido Masera, Maurizio Martina, George Suciu, Mari-Anais Sachian, Nicoleta Capbun, Alexandru Șneapotă, Călin Zamfir, Anca Burlacu-Zane, Simona Costinescu, Ambily Suresh, Diego Gigena-Ivanovich, Honorius Gâlmeanu, Mihai Munteanu, Alexandru Drîmbărean, Darshak Sheladiya, Jan Reinhard, Florian Krebs, David Engraf, Holger Blasum, Mattia Paladino, Daniele Gregori, Federico Proverbio, Jan Kastil, Pavel Zaykov, Alexander Schober, Rainer Buchty, Mladen Berekovic, Amrit Sharma Poudel, Lukas Groth, Saleh Mulhem, Emanuele Valpreda, Andrea Zunino, Luigi Feola, Samuel Matea, Cosmin Moisa, Andrei Stan, Alexandru-Tudor Popovici, George-Iulian Uleru, Cristian-Tiberius Axinte, Cosmin-Andrei Popovici, Daniel Gracia Pérez, Sylvain Girbal, Jérôme Quévremont, André Sintzoff, Angelo Garofalo, Alessandro Nadalini, Fatma Jebali, Caaliph Andriamisaina, Florian Egert, Maurizio Capra, Alessandro Aimar, Valerio Venceslai, Francesco De Maldé, Maria Elena D’Agostino, Gabriele Magnani, Davide Baroffio, Andrea Galimberti, Carlo Brandolese, Giancarlo Storti Gajani, Costin-Emanuel Vasile, Vlad-Gabriel Serbu, Alexandra-Mihaela Enescu, Radu Hobincu, Calin Bira, Elijah Seth Cishugi, Marco Ottavi, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2025 conference,

Minutiae Extraction Optimization for ARM and RISC-V, Andreea Violeta Pascociu, Andrei Eduard Solomon, Csaba Zoltán Kertész, Cătălin Bogdan Ciobanu, in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025),

Adversarial Attacks Detection for Self-Driving Cars using GPUs, Ștefan Cristian Jarcău, Ionuț Alexandru Oprea, Alexandru Mihai Andrei, Robert Ionuț Duca,Bogdan Valentin Floricescu, Cătălin Bogdan Ciobanu, Lucian Mircea Sasu, Sorin Mihai Grigorescu, in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025),

Scalable 16-N point FFT Accelerator, Răzvan Stancu, Mihai Gologanu, Alexandru Pușcasu, Cătălin Bogdan Ciobanu,Octavian Buiu, in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025),

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL, Robin Sehm; Christian Ewert; Rainer Buchty; Mladen Berekovic; Saleh Mulhem, Euromicro Symposium on Digital System Design,

HashTAG With CALM: Low-Overhead Hardware Support for Inter-Task Eviction Monitoring, Pablo Andreu, Pedro López, Carles Hernández, IEEE Transactions on Parallel and Distributed Systems, https://ieeexplore.ieee.org/abstract/document/11269742

TinyATD: Compressing Auxiliary Tag Directories using tag hashing and set-sampling, Pablo Andreu, Pedro Lopez, Carles Hernandez, Journal of Systems Architecture, https://www.sciencedirect.com/science/article/pii/S1383762125003169

An open-source methodology to emulate transient faults in ASIC storage cells using AMD Ultrascale+ FPGAs, Ilya Tuzov, David de Andrés, Juan-Carlos Ruiz, Carles Hernández, ACM Transactions on Reconfigurable Technology and Systems, https://doi.org/10.1145/3797884

Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs, Peccia, Federico Nicolás, Haxel, Frederik, Bringmann, Oliver, IEEE International Conference on Computer-Aided Design, https://zenodo.org/records/18433357

Porting OpenEMS and Apache StreamPipes energy management software to freshly developed RISC-V system software stacks, Holger Blasum1, Darshak Sheladiya1, Jan Reinhard1, Florian Krebs1, David Engraf1, Samuel Ardaya-Lieb2, Frederik Haxel3, Dominik Riemer4, George Suciu5, Mari-Anais Sachian5, ERTS, https://hal.science/ERTS2026/hal-05513744v1

Leveraging a Superscalar CVA6 to implement NTT instructions for Post-Quantum Cryptography, Côme Allart, Kévin Guilloux, Jean-Roch Coulon, André Sintzoff, Olivier Potin, and Jean-Baptiste Rigaud, CASCADE 2026,

Safe-NEureka: a Hybrid Modular Redundant DNN Accelerator for Satellite Onboard AI Processing, Riccardo Tedeschi, Luigi Ghionda, Alessandro Nadalini, Yvan Tortorella, Arpan Suravi Prasad, Luca Benini, Davide Rossi, Francesco Conti, Under review,

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems, Natalie Simson, Ares Tahiraga, Wolfgang Ecker, MBMV 2024, n/a

RISC-V Reuse Made Easy by Interface Generation and Integration Automation, Ares Tahiraga, Said Llukaj, Wei Zhao, Endri Kaja, Sebastian Prebeck, Wolfgang Ecker, DVCon US 2026, n/a

A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V, Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker, DFT 2024, n/a

Improving Design Generation by Interface Configuration Propagation, Natalie Simson, Paritosh Kumar Sinha and Wolfgang Ecker, MBMV 2025, n/a

Platform-Aware RTL Generation: Bridging the Gap between Design and Implementation, Mohamed Badawy, Nicolas Gerlin, Paritosh Kumar Sinha, Endri Kaja, Jad Al Halabi, Stephanie Ecker, Natalie Simson and Wolfgang Ecker, MBMV 2025, n/a

Rustifying Embedded Software Development: A Model-Based Code Generation Approach for Auto-Generation of C and RUST, Raphael Kunz, Mayuri Bhadra, Stephanie Ecker and Wolfgang Ecker, MBMV 2025, n/a

Characterising Physical Memory Access Pattern Impact on RISC-V Softcore Performance: A Microbenchmark Study, Hsin-Kun Lin, Wadid Foudhaili, Rainer Buchty, Mladen Berekovic & Saleh Mulhem, LNCS 16514, ARC 2026, n/a

Runtime Monitoring for Safe Autonomous Mobile Robots, Sven Mehlhop, Frank Oppenheimer, Forum on specification & Design Languages, n/a

Applications of Tiny RISC-V - Invited paper, Jaume Abella, Sergi Alcaide, Eric Rufart, Leonidas Kosmidis, Catalin Bogdan Ciobanu, Alexandru Puscasu, Razvan Stancu, Octavian Buiu, Costin-Emanuel Vasile, ACM International Conference on Computing Frontiers, 2026, https://hdl.handle.net/2117/468406

On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, Embedded Real Time Systems (ERTS) 2026 conference, https://hal.science/hal-05513236

Embedded Streaming Hardware Accelerators Interconnect Architectures and Latency Evaluation, Axinte, Cristian-Tiberius, Andrei Stan, and Vasile-Ion Manta, Electronics, n/a

RiscADA: RISC-V Extension for Optimized Control of External D/A and A/D Converters, Popovici, Cosmin-Andrei, Andrei Stan, Nicolae-Alexandru Botezatu, and Vasile-Ion Manta, Electronics, https://github.com/cosminandreipopovici/cva6/tree/kcu116

In(Si)Sim RVE–Lightweight Open-Source Framework for Functional Verification of RISC-V Extensions, Popovici, Cosmin-Andrei and Stan, Andrei and Vieriu, George-Emil and Manta, Vasile-Ion, IEEE Access, https://github.com/cosminandreipopovici/InSiSim_RVE

Customization of RISC-V Core for Field-Oriented Control Algorithm, Jiri Gallo, Jan Kastil, Jan Povolny, Simon Zossak, Martin Kostal, Petr Zelinka, Vaclav Simek, https://dsd-seaa.com/,

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA, Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese, Machine Learning and Principles and Practice of Knowledge Discovery in Databases, https://arxiv.org/abs/2605.12217

Compatibility Ratio as a Guideline for Hardware/DNN Co-Design of Embedded Accelerators, Lukas Groth, Andrija Neskovic, Rainer Buchty, Mladen Berekovic, Saleh Mulhem, ACM Transactions on Embedded Computing Systems

Forging Robust Building Blocks for Next-Gen RISC-V Chips: Virtual Repository and IP Card, Cătălin Bogdan Ciobanu, Francesco Conti, Cairo Caplan, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Davide Schiavone, Dominik Baumann, Alexandru Pușcașu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, Jörg Walter, Frank Oppenheimer, Gianvito Urgese, Teodoro Urso, Roberto Bosio, Alessio Burrello, George Suciu, Mari-Anais Sachian, Nicoleta Capbun, Robert Florescu, Simona Costinescu, Ambily Suresh, Florian Lorber, Honorius Gâlmeanu, Mihai Munteanu, Szilard Hegedus, Darshak Sheladiya, Florian Krebs, Henrik Theiling, Mattia Paladino, Daniele Gregori, Federico Proverbio, Jan Kastil, Alexander Schober, Rainer Buchty, Mladen Berekovic, Amrit Sharma Poudel, Saleh Mulhem, Emanuele Valpreda, Andrea Zunino, Luigi Feola, Samuel Mătea, Cosmin Moisa, Cristian Perian, Andrei Stan, Alexandru-Tudor Popovici, Cosmin-Andrei Popovici, George-Emil Vieriu, Daniel Gracia Pérez, Sylvain Girbal, Jérôme Quévremont, André Sintzoff, Fatma Jebali, Caaliph Andriamisaina, Florian Egert, Maurizio Capra, Alessandro Aimar, Valerio Venceslai, Francesco De Maldé, Maria Elena D’Agostino, William Fornaciari, Gabriele Magnani, Davide Baroffio, Andrea Galimberti, Carlo Brandolese, Giancarlo Storti Gajani, Costin-Emanuel Vasile, Radu Hobincu, Alexandra-Mihaela Enescu, Calin Bira, Elijah Seth Cishugi, Marco Ottavi, Esther Soriano, Ester López, Vicente Nicolau, ..., https://dsd-seaa.com/

The Chips Joint Undertaking invited ISOLDE, TRISTAN, RIGOLETTO and REBECCA to participate in the EFECS 2026 project exhibition, taking place on 2-3 December 2026 at Messukeskus Helsinki Expo and Convention Centre, Finland.

And ISOLDE will be there. Meet you in Helsinki.

The ISOLDE consortium recently returned to Munich on February 3-4, 2026, for a project meeting. Bringing together partners from across Europe both in person and online, this gathering once again proved the collective expertise and dedication driving ISOLDE’s mission to develop high-performance RISC-V processing systems for key sectors such as automotive, space, and IoT.

As ISOLDE officially enters its home stretch, this two-day session was focused on strategic alignment. Consortium members shared comprehensive updates on their progress and defined the concluding steps necessary to cement the project's objectives.

A core objective of this meeting was syncing our final project activities. With the finish line in sight, partners participated in targeted workshops to ensure that all independent work packages integrate seamlessly into the final deliverables. These collaborative sessions allowed the team to tackle remaining technical challenges and guarantee that the project's approach culminates in a robust outcome.

The success of this meeting would not have been possible without the active participation and engagement of all consortium members. A big thank you to everyone who contributed their time, and work, whether attending in Munich or connecting virtually.

As we push forward toward our ultimate goal of delivering customizable, high-performance IPs hosted on European servers, we are more aligned than ever to successfully conclude this journey together.

Stay tuned for our final results and upcoming updates as ISOLDE crosses the finish line!

This year, the Austrian RISC-V community launched a collaborative initiative aimed at increasing the visibility and impact of the RISC-V ecosystem. The RISC-V meetup, chaired by Daniel Müller-Gritschneder (TU Wien) and Willibald Krenn (Silicon Austria Labs) has gained strong backing from industry leaders such as NXP Semiconductors and Infineon. Their shared goal: to create a strong platform for exchanging knowledge and fostering deep technical dialogue across academia and industry.

At the second Austrian RISC-V Meetup at Silicon Austria Labs (SAL), Marcel Medwed from NXP in Austria presented the latest developments in microcontroller (MCU) security. His talk focused on how RISC-V instruction set extensions are shaping the future of both physical and logical protection for embedded systems. These efforts are part of the ISOLDE project under the Chips Joint Undertaking, which aims to expand and industrialize the European RISC-V ecosystem.

The goal? To compete with proprietary alternatives by delivering high-performance, secure processing platforms tailored for automotive, smart cities, mobility, and logistics.

Understanding MCU Vulnerabilities and Attack Vectors

Embedded systems face a range of attacks, from clock and power glitches that can cause timing violations, to memory vulnerabilities like buffer overflows. These attacks can lead to skipped instructions, faulty data, privilege escalation, and even arbitrary code execution.

The challenge lies in designing security mechanisms that are both robust and efficient, minimizing impact on code size and hardware footprint.

ISOLDE’s Cocktail of Countermeasures

To address these threats, the ISOLDE project has developed a comprehensive suite of RISC-V extensions and custom security mechanisms:

Key Takeaways and Conclusion

Security for embedded systems must be both effective and lightweight, ensuring robust protection without unnecessarily increasing code size. By leveraging RISC-V instruction set extensions and custom mechanisms, developers can implement targeted and efficient security features. Within the ISOLDE project, a comprehensive "cocktail" of countermeasures has been developed to address both fault-based and software-based attacks, providing a holistic approach to embedded system security.

November 2025 – Advancing its mission to transform Europe's technological landscape, the ISOLDE project is delivering major advancements in high-performance embedded computing, safety, and security through open-source RISC-V processor technology. Bringing together a consortium of 37 partners and 2 associated partners from leading European research institutions and industries, ISOLDE is laying the groundwork for digital sovereignty and semiconductor independence. Funded under the Chips Joint Undertaking (Chips JU) within Horizon Europe, the project is accelerating digital transformation while supporting Europe’s transition toward a green, climate-neutral, and digitally autonomous future.

Driving Innovation in European High-Performance Computing, Safety and Security

The ISOLDE project (High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems) is advancing European-designed high-performance RISC-V-based CPUs and IP blocks, including accelerators, to Technology Readiness Level (TRL) 8 by project completion. These open-source processor architectures and accelerators will be showcased by demonstrators for key European industries such as automotive, space, and IoT. About two years after completion, first ISOLDE high-performance components are expected to be integrated into industrial-grade products.

To ensure sustainability and accessibility, ISOLDE is initiating an industrial-grade open-source support ecosystem for development, verification, and maintenance. In addition, customizable IPs will be distributed through secure, industrial-grade repositories, ensuring long-term availability and reinforcing the European Union’s commitment to digital sovereignty.

Key Achievements Over Two Years

Over the past two years, ISOLDE has reached important milestones in advancing RISC-V-based high-performance computing, safety, and security. These achievements pave the way for Europe’s leadership in open-source semiconductor technology and digital sovereignty. Highlights include:

• Development of methodologies that enable seamless integration of open-source and proprietary IPs, ensuring effective interoperability. This approach allows organisations to benefit from open collaboration while protecting proprietary innovations.

• Definition and first implementation of demonstrators across critical sectors such as space, automotive, Smart Home, and cellular IoT. These will showcase RISC-V-based architectures by integrating IPs from multiple partners and running a complete software stack.
• Consolidated documentation of requirements and specifications for both the IPs under development and the demonstrators to be integrated. This material, publicly available, promotes transparency and invites the broader community to contribute, review, or adopt project results. By making documentation accessible, ISOLDE supports future developments within the open-source ecosystem, fostering interoperability and consistency across systems and tools.
• Joint initiatives with the TRISTAN project, strengthening the RISC-V ecosystem, including participation in the RISC-V Summit Europe, joint publications, and the creation of a shared repository for IP distribution.

A Breakthrough in European Semiconductor Independence

By strengthening the European RISC-V ecosystem, ISOLDE is making a decisive contribution to unifying and advancing an industry-backed, homegrown open-source architecture for high-performance embedded computing.

As ISOLDE enters its final phase, efforts will focus on tapeout-ready designs, FPGA-based prototypes, expanded industrial collaborations, and preparing the deployment of its solutions. The project’s progress shows that Europe is not only capable of competing in the global semiconductor industry but is also taking a leadership role in open computing innovation.

For more information about ISOLDE and its achievements, visit www.isolde-project.eu.

ISOLDE's Presentation slot is scheduled for: 

Thursday, 4 December 2025

13:30 – 13:45, during Networking Lunch

at Booth number 7.

About: EFECS 2025 is the premier European Forum for Electronic Components and Systems, dedicated to advancing the sector’s growth and innovation. Taking place in Malta on December 3-4, 2025, this event brings together industry leaders, policymakers, researchers, and innovators to strengthen Europe’s strategic leadership in semiconductor technology.

The ISOLDE project, funded by the Key Digital Technologies Joint Undertaking (KDT JU), aims to develop European high-performance RISC-V-based CPUs, achieving functional and non-functional improvements to compete with proprietary alternatives or surpass them. Project partners from leading EU universities and companies will develop advanced architectures, novel accelerators, and reusable IPs, forming a robust compute infrastructure for applications in automotive, industrial, and aerospace domains. The ISOLDE project seeks to establish an European sovereignty in semiconductors, closing the confidence gap, and driving adoption through prototype solutions, documentation, and benchmarks.

Within this project, a demonstrator is developed targeting the space use-case, to showcase the IPs developed in ISOLDE and aiming at revolutionizing onboard computational capabilities for space applications by leveraging RISCV cores and accelerators, integrated with an advanced software layer, to create a hardware and software platform capable of meeting the dual challenges of demanding computing and memory requirements and the harsh environmental constraints of space.

A key innovation of the project is to harness the CVA6 processor family and tensor accelerators, all connected through the open standard BUS protocol AXI4, to enable processing capabilities closer to the sensor and support the development of onboard inference capabilities. Compute intensive applications are offloaded to dedicated accelerators controlled by the Cheshire system host and can communicate directly with the memory through dedicated DMAs, relieving the host from unnecessary CPU cycles. This approach aims to transform traditional workflows, where satellite data, such as Earth observation images, undergo initial preprocessing onboard before being transmitted to ground stations for high performance computing. By bringing these processing steps onboard, the project not only minimizes uplink and downlink requirements, but also accelerates real-time decision-making and enhances satellite autonomy.

The space demonstrator targets a low-Earth orbit satellite use-case, inspired by the Sentinel-2 mission, and  encompasses a broad range of applications, such as Earth observation, avionic functionalities and attitude orbit control (AOC), and telemetry processing for fault detection, identification, and recovery (FDIR). Beyond these traditional domains, the ISOLDE space demonstrator focuses on artificial intelligence (AI) models to further enhance spacecraft autonomy. These models will be crucial for applications such as wildfire detection from hyperspectral images captured by the multi-spectral instrument (MSI) and FDIR using telemetry data from the Attitude Control System (ACS). The performance of these AI algorithms will be evaluated on the new hardware, showcasing their potential to redefine the role of onboard computing in space systems.

About Leonardo

Leonardo is a global industrial group that creates multi-domain technological capabilities in the Aerospace, Defence and Security sector. With over 60,000 employees worldwide, the company has a significant industrial presence in Italy, the UK, Poland and the US. It also operates in 150 countries through subsidiaries, joint ventures and investments. A key player in major international strategic programmes, it is a technological and industrial partner of governments, defence administrations, institutions and companies. In 2024, Leonardo recorded consolidated revenues of €17.8bn, new orders for €20.9bn and invested €2.5bn in R&D. Innovation, continuous research, digital industry and sustainability are the pillars of its business worldwide.

Role of Politecnico di Milano in ISOLDE

In the context of the ISOLDE project, Politecnico di Milano (PoliMi) develops approximate computing technologies at the hardware and software level, cryptographic accelerators, and efficiency enhancements for real-time computing. The proposed advances are applied to the Space demonstrator RISC-V-based platform.

TAFFO and the ISOLDE architectural extensions

Approximate Computing is an emerging paradigm that attempts to improve the energy efficiency of computation, a critical issue for battery-powered embedded systems as well as to address the increasing energy footprint of ICT worldwide, by trading off some of the computation accuracy.

Briefly, in any computer system, all computations are performed with a certain degree of accuracy, i.e., on a fixed number of digits (more precisely, of bits). This number of digits is usually vastly oversized with respect to the actual ranges of the numeric values computed, to minimize the risk of errors.

The TAFFO framework enables the reduction of the data size, as well as the switching between different types of data representations (e.g., floating point, fixed point, etc.) to trade off accuracy that is not actually needed by the computation for lower energy consumption, obtained by employing custom hardware, such as the customized floating point unit also developed by PoliMi, or by adapting to the available hardware characteristics (e.g., switching to fixed point when a hardware floating point unit is not available at all).

With the seTHet and luTHet extensions developed in ISOLDE, TAFFO is also able to efficiently exploit the memory subsystem of an heterogeneous system, by tuning the precision in accordance to the available direct memory access bandwidth and by tabulating costly trigonometric functions instead of computing them.

Considering a Sobel edge detection, a different tuning of the available memory for trigonometric function tabulation minimally affects the quality of the output yielding a 30× speedup and, consequently, a reduction of the total energy by the same factor. The framework then selects the best solution according to the required quality and the available memory.

Politecnico di Milano

Politecnico di Milano is the foremost technical university in Italy, with over 45,000 students in engineering, architecture and design, and is ranked among the first in the European Union according to the 2025 QS ranking. The university also serves as a technology development and transfer hub, with over 100 spin off companies and over 3000 patents. Within Horizon Europe, it has obtained funding for over 150M€ in over 300 projects, including 36 ERC grants.

The HEAP laboratory of the Department of Electronics, Informatics and Bioengineering is a cross-disciplinary research team of around 20 people with skills covering Embedded and Cyber Physical Systems, Design Methodologies, Low-power Design of Software and Hardware, Compiler Construction, and Embedded Systems Security and Data Privacy.

The group has been active for over two decades in designing architectures and in developing methodologies and prototype tools to support the automation of different design phases of advanced embedded and computing systems.

The summer period has been an important time for the ISOLDE project, marked by key milestones and fruitful exchanges across Europe.

In early July, representatives of our Work Package Leaders attended the official project review meeting in Brussels. This review was a significant moment to reflect on the progress made so far, showcase the results achieved, and receive constructive feedback from the EC reviewers. We are proud to share that the outcome was very positive, confirming that ISOLDE is on the right track to deliver on its ambitious objectives. The reviewers also provided valuable recommendations, which will help us shape our next steps with even greater precision and impact.

Later in the month, members of the consortium came together in Munich for an in-person meeting. This gathering offered the perfect setting to discuss in detail the future work plan, align our strategies with the recommendations from the review, and strengthen our collaborative spirit. The agenda combined technical discussions with opportunities for open exchange, fostering both focused work and creative thinking.

Our time in Munich was not only about work — we also took the chance to organise a social programme, allowing team members to connect beyond the meeting room. These moments of informal interaction help reinforce the trust, understanding, and shared commitment that underpin the success of the project.

An additional highlight of the Munich meeting was a joint workshop with four sister projects: TRISTAN, REBECCA, RIGOLETTO, and Scale4Edge. This collaborative session was designed to learn more about each project’s goals, approaches, and progress, while identifying potential synergies and areas for alliance. Such cross-project exchanges are essential for building a strong research and innovation ecosystem, ensuring that efforts complement rather than duplicate each other, and opening the door to new opportunities for cooperation.

The combination of a successful project review, a productive consortium meeting, and a great workshop with related initiatives made July a month of momentum for ISOLDE. With renewed energy and clear direction, we look forward to implementing the next phase of our work.