| CVE2 | Solderpad | In progress | A single-issue 2-stage pipeline embedded class of RISC-V CPUs |
| RVB / RVP Standard Extensions support for CV32E40P core | Solderpad | In progress | Development of light-weight RISC-V Instruction Set Architecture (ISA) extensions to improve the energy efficiency of low-bit-width mixed-precision integer arithmetic |
| Extensions to the micro-architecture of CV32E40P core | Solderpad | In progress | |
| VSRV: Simple 32-bit RISC-V Linux-Capable Core | Solderpad | Released | 32-bit compact RISC-V processor that runs off-the-shelf protocols under latest linux kernel |
| CVA6 | Solderpad | In progress | A configurable family of RISC-V application/embedded cores targetting FPGA and ASIC technologies |
| RVV coprocessor for CVA6 | Solderpad | Released | RVV (vector) co-processor for CVA6 with support for low precision integer arithmetic (down to 8-bit vector data types) and multi-precision floating-point operations |
| Timing Channel Protection | Solderpad | Released | Increasing the security features of CVA6. In particular, it provides support for timing channel protection in CVA6 |
| UVM env and testbench for the CVA6 core | Solderpad | Finished | UVM environment for the verification of RISC-V cores, supporting a thorough verification of the CVA6 (and other) cores to reach TRL-5 |
| Compression and decompression of digital waveforms | TBD | In progress | Custom instructions for CV32E40X core to improve the performance of real-time compression and decompression of digital waveforms |
| TraceUnit | TBD | In progress | Architecture and design of RISC-V Trace IP |
| Hypervisor | Solderpad | Released | Hypervisor support for CVA6 complying with the RISC-V hypervisor extension specifications |
| Riviera: RISC-V ISA Extensions for NFC Applications | LA_OPT_NXP Software License | Design and Verification completed | CV-X-IF compliant RISC-V Co-processor for a NFC Receiver decoder custom DSP acceleration |
