The Digital Circuits and Systems Group of ETH Zürich has been working on open-source hardware since 2013 under the PULP platform banner (https://pulp-platform.org/). As a founding member of the RISC-V foundation, ETH Zürich has designed some of the most commonly used RISC-V processor cores, such as CVA6/Ariane, CV32E40P/RI5CY, and Ibex/ZeroRiscy. ETH Zürich also has significant experience in ASIC design, having implemented over 50 ASICs manufactured using PULP-based open-source HW (http://asic.ethz.ch/). ETH Zürich is excited to bring this experience to the ISOLDE project and work with partners on establishing high-performance RISC-V-based computing systems that can be used in industrial quality products.
Our world has an endless appetite for additional computing power that triggers the digital revolution. At the same time, the raw electrical power needed for computing has reached levels that can not sustain this growth rate anymore. Simply put, the world needs more efficient ways of performing computing, doing more of it while spending less energy to do so.
Classical (von Neumann) computers have not changed much since their inception, and in very simplified terms, computer programs fetch simple instructions from memory that tell them what to do and then go fetch operands from memory, perform the operation, and then copy the result back to memory.
One of the ways to improve the efficiency of computing is to reduce the effort to perform this part of the operation. In regular (scalar) processing, the instruction tells the processor what to do with one word of data (usually 64 bits). So, if an array of data is being processed (with, for example, 1000 elements), the processor repeats the same task for all the elements in the array. Vector processing tries to take advantage of this and specifies operations on large vectors. A simple vector instruction can be used to schedule 1000 additions instead of executing 1000 individual additions separately. As long as you have many such operations, you can perform them more efficiently.
To this extent, the RISC-V ISA defines the RISC-V Vector extension (RVV), a set of instructions to perform vector operations (https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), and ETH Zürich has been investigating different approaches on how to a) implement such vector engines and b) pair them with existing processors to extend their capabilities.
The Ara design started when the RVV specification was still in its early stages and has been designed to work in tandem with the CVA6/Ariane core. Versions of this openly available core have already been taped out, as can be seen in Figure 1.
Figure 1 - Die shot of the Yun chip. Highlighted: CVA6, the scalar processor with its level-1 cache memories, and Ara’s four vector lanes with their Vector Register File (VRF) chunks. In the upper-right corner: peripherals and main level-2 scratchpad (SP) memory.
Ara was designed to efficiently accelerate the computation of long vectors and showed the potential of RVV by reaching almost peak performance on ubiquitous kernels such as matrix multiplications and convolutions, which are largely used in machine learning tasks. Figure 2 shows the power breakdown of combined CVA6/Ara executing a large matrix multiplication that can take advantage of the vector extensions.
Figure 2 - Ara Power consumption breakdown during a matrix multiplication. Most of the power is spent in the vector floating-point unit (VMFPU), which is where the core computation is done. The vector architecture helps keep the power related to the fetch of the instruction low, as testified by the small 2.4% of the budget taken by CVA6’s instruction cache.
A second approach the group has taken is to explore how the vector processor architecture maps to the embedded world by developing a tiny and efficient integer-only 32-bit vector accelerator named Spatz (Figure 3) that can be integrated into the Mempool many-core system. Spatz, as opposed to Ara, was coupled with a tiny and agile scalar processor called Snitch and further showed the potential of RVV in a more constrained processing domain.
Since the first Ara prototype, ETH Zurich has explored different ways of coupling vector accelerators to scalar processors, and many different interfaces were changed over time, with a particular interest toward the OpenHW Group’s X-interface, already used with an early design of Spatz. Currently, the open-source Ara is being actively developed following the last development of the specifications.
Figure 3 - Spatz architecture. Spatz works in tandem with the Snitch processor by means of the X-interface.
As mentioned before, processors usually operate at a fixed size of words (usually 64-bit), which means that any value that is computed is represented by 8 bytes in memory. There are some applications where the range of numbers that are used in computing is quite limited (for example, 0-100), and the same amount of memory can be used to represent multiple different numbers, significantly reducing the memory needs and the computation complexity, with a reduction of the overall energy needed to perform these operations.
To be effective and efficient, a computing system needs to handle different types of number representations. These multi-precision computing blocks allow computing to take place in the most efficient number representation while allowing the full range of capabilities to remain intact.
ETH Zürich has been actively working on exploring efficient arithmetic computing units that can support multiple number formats, mainly through the fpnew, a RISC-V-compliant Floating-Point Unit (FPU) originally developed with multi-precision capabilities as one of its fundamental goals and now maintained by OpenHW Group under the name cvfpu. Its modular multi-precision-ready design allows for computing floating-point operations from 64-bit to 8-bit floating-point data. It also supports alternative formats for 16 and 8 bits, more and more used in the machine learning domain.
Vector processing and multi-precision capabilities are fundamental steps toward fast and efficient processing in an era in which focusing the power where it is really needed, without any waste, is paramount. To this extent, ETH Zurich is working on fully supporting the cvfpu multi-precision capabilities on the Ara vector processor to unleash even higher energy efficiency during the computation.
In ISOLDE, we aim to apply this know-how to multi-precision Vector processing units paired with RISC-V cores to improve the efficiency of the target use cases and provide Europe and the whole open-source community at large with new tools to tackle the upcoming computational challenges.
The ISOLDE project is dedicated to advancing the development of high-performance RISC-V processing systems, with the goal of empowering European industries and fostering digital sovereignty of the EU. By the completion of the project, ISOLDE aims to have systems and platforms that will be demonstrated in major European application areas, including automotive, space, and IoT. Moreover, it is expected that two years after completion, the high-performance components developed by ISOLDE will be integrated into industrial-quality products. Among the demonstrators envisioned in the project, E4 Computer Engineering will focus on developing a demonstrator in the space sector.
The Space Demonstrator is one of the key components of the project, which involves constructing a FPGA and a ready-to-tapeout multicore SoC design specifically designed for space applications. The Space Demonstrator will be used to validate the feasibility and performance of RISC-V-based SoCs in space environments. This will pave the way for wider adoption of RISC-V in future space missions. The integration of a RISC-V processor into the Space Demonstrator represents a pivotal advancement in spacecraft capabilities. RISC-V's open-source architecture brings several advantages to space applications, including reduced costs due to the absence of licensing fees and adaptability to meet specific space requirements.
E4 plays a crucial role in the development of the space demonstrator, ranging from a preliminary definition of the requirements for the demonstrator and extending to the implementation of the FPGA and the development of test methodologies to validate correctness and functionality of the implementation. E4 will also facilitate the synchronization of software design with the implementation and testing of the demonstrator and, additionally, will collaborate on the development of V&V methodologies and APIs. Our involvement spans the entire design of this demonstrator, from its inception to its completion, with the goal of creating a high-performance, reliable, and secure demonstrator that illustrates RISC-V processing systems for space applications.
As the ISOLDE project progresses, the Space Demonstrator will serve as a platform to validate the feasibility and performance of RISC-V-based SoCs in space environments. This validation process will contribute to the broader adoption of RISC-V in future, fostering the development of a robust European RISC-V ecosystem.
According to the European Union's energy and climate targets, greenhouse gas emissions are to be reduced to zero by 2050. The Paris Climate Agreement calls for global warming to be limited to 1.5 degrees Celsius. Achieving these targets requires a switch to renewable energies such as wind power and photovoltaics. This requires a reform of the energy industry, which poses technological challenges for European countries.
In terms of dimensioning and control, the current electricity grid is designed for a small number of centralised, controllable power plants on the one hand and static consumers on the other. However, the proportion of decentralised, emission-free energy generation plants is constantly increasing. Many of these systems do not supply their energy constantly, but with large fluctuations throughout the day. Cushioning such fluctuations completely with batteries is not realistic, as this would require gigantic storage capacities. At the same time, single and multi-family homes, which represent a large proportion of energy consumers, can no longer be modelled using static load profiles alone. Interconnected, controllable devices such as heat pumps, battery storage systems and smart household appliances are becoming increasingly widespread in residential properties, offering flexibility in consumption. With the strong growth of electromobility, the electric car is another flexible consumer that can be used temporarily as a buffer storage or energy supplier. It is therefore important to use this flexibility and adapt the consumers to the fluctuating generation in the best possible way through energy optimisation.
Making a contribution to meeting the Paris climate targets through energy efficiency has been the goal of Consolinno Energy GmbH since it was founded in 2017. The young GreenTech company from Regensburg, Germany, realises efficient energy solutions with innovative technologies (AI, IoT, Cloud, Edge) and smart energy planning. Consolinno relies on hardware systems developed in-house, customised software and storage and visualisation in the cloud. AI plays a decisive role here with schedule management. When used in neighbourhoods, sector coupling takes place: components such as combined heat and power plant (CHP), photovoltaic (PV) and battery are interconnected and automated for the best possible energy efficiency. The solutions are part of smart home automation as well: the devices therefore also regulate the energy flow in single-family homes. Consolinno has developed the manufacturer-independent energy manager Leaflet HEMS (home energy management system) for this purpose. The Leaflet HEMS is also equipped for future topics such as grid serviceability and dynamic tariffs.
Credits: Consolinno Energy
The ISOLDE research project is focussing on the further development of the RISC-V instruction set architecture (ISA). This ISA could represent serious competition for the dominant ARM and x86 architectures in the future and has the special characteristics of being modular and open source. This means that with RISC-V, any company can in principle purchase its own customised microprocessor unit (MPU) or even develop one itself. Many partners in ISOLDE take care of the design or improvement of the RISC-V architecture or associated extensions. Consolinno Energy GmbH is taking part in the project in the role of the user and is investigating whether a RISC-V processor could be used to develop a real, competitive IoT product in the energy sector.
As part of the ISOLDE project, Consolinno therefore wants to investigate the feasibility of a completely open-source energy management system based on RISC-V, embedded Linux and OpenEMS. The aim is also to investigate whether it is possible to transfer an existing ARM-based software stack to a RISC-V processor. In addition, Consolinno wants to explore the possibilites of optimisation of energy systems on the edge in greater depth and, if possible, make use of hardware accelerators on the RISC-V platform. The aim is to show that RISC-V is not just a playground for science and research, but may also be used as a reliable building block for companies in the private sector.
Links:
Consolinno Energy GmbH: https://consolinno.de
OpenEMS: https://openems.io
Are you familiar with the medieval love story about Tristan and Isolde? Well, this is not it. We are talking about ISOLDE as in HIgh Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems. This project kicked off in early 2023 and engages more than 40 partners from 9 different European countries. ISOLDE aims to support Europe’s digital transformation within various sectors to speed up the transition towards a green and digitally autonomous Europe. Central to this ambition is the goal of strengthening the design capacity across the EU.
To achieve these ambitious goals, the members of the project will create high-performance, industrial-grade processing systems and platforms based on RISC-V. Codasip’s role is to customize our existing RISC-V cores for a selected set of compute-intensive automotive applications. Firstly, we are working closely with other partners in the project to define the requirements for the tailoring of the computing architecture. Next, we will focus on application analysis and processor customization. We will of course also do extensive work on benchmarking, parametrization, and verification.
So how do we customize a processor to make it more efficient? One very effective way is to add custom instructions. But there is more to it. In addition, you can use techniques such as increasing the data throughput, parallelizing operations, or managing specific data types. Also, you can add application-related features. At Codasip, we call this Custom Compute.
Custom Compute enables innovation for sustainability. You can learn more in our recent blog post on saving the planet, one byte at a time.
How to design products differently to reduce the carbon footprint, here using a mobile phone as an example
A key pillar of Codasip Labs is the commercialization of innovation. This is a perfect match with the aims of the ISOLDE project.
Technology readiness level (TRL) is a method for estimating the maturity of a technology. TRLs were first introduced by NASA and have been adopted, and adapted, by the European Commission. The commission has defined the following 9 TRLs:
TRL 1 | basic principles observed |
TRL 2 | technology concept formulated |
TRL 3 | experimental proof of concept |
TRL 4 | technology validated in lab |
TRL 5 | technology validated in relevant environment (industrially relevant environment in the case of key enabling technologies) |
TRL 6 | technology demonstrated in relevant environment (industrially relevant environment in the case of key enabling technologies) |
TRL 7 | system prototype demonstration in operational environment |
TRL 8 | system complete and qualified |
TRL 9 | actual system proven in operational environment (competitive manufacturing in the case of key enabling technologies; or in space) |
Extract from Part 19 - Commission Decision C(2014)4995
Why am I telling you about TRLs? Well, because the ISOLDE project intends to provide RISC-V-based platforms at least at TRL 7. This means that at the end of the project in 2026, the participants will not only have created proof of concepts. Rather, we will actually have validated and demonstrated the solutions in an operational environment. This means that the project will deliver solutions that can be
used in industrial quality products. The outcome is expected to be part of actual systems within a couple of years from the project’s end date. Key application domains for the technology include automotive, space, and IoT. Surely with this ambitious aim, ISOLDE will further accelerate RISC-V commercialization.
An interesting aspect of ISOLDE is the included requirements to support European digital sovereignty. All participating partners are in Europe. In the end, the resulting customizable IP cores will be hosted on European servers. The more than 40 involved organizations represent large parts of EU critical chip infrastructure. This ecosystem is currently establishing the requirements and specifications for the building blocks that the project will develop.
By the time the project comes to an end, ISOLDE will have delivered a major contribution to the RISC-V ecosystem. Particularly, the project will benefit embedded high-performance computing, and contribute to the design capacity across the European chip industry.
LEARN MORE ABOUT PROCESSOR CUSTOMIZATION
Note: The project “ISOLDE” has received funding from the European Union HE Research and Innovation programme under grant agreement No 101112274. Codasip s.r.o, as a Czech participant in this project, is supported by the Ministry of Education, Youth and Sports.
Last week, the ISOLDE consortium met in Valencia in their first progress meeting after the kick-off to share the latest updates of the project. The Polytechnic University of Valencia was the perfect location for this event which hosted more than 50 attendees of the different organizations that take part in this distinguished Horizon Europe project.
This meeting marked significant strides towards ISOLDE’s goal of developing high-performance RISC-V processing systems and platforms which will revolutionize key European application domains such as automotive, space, and IoT.
During two days of full activity, the ISOLDE team converged to discuss and strategize the path forward. With experts from diverse organizations and markets, discussions were enriched by a multitude of perspectives, fostering a collaborative spirit essential to the success of the project.
This first progress meeting served as a platform to unveil the progress achieved in the past months for the development of high-performance RISC-V processing systems and platforms. Task leaders showcased the advancements of each work package and the future activities that will be performed in the next months. Attendees participated in meaningful discussions to find all possible ways of collaboration and achieve the best result.
With a focus on key European application domains, including automotive, space, and IoT, ISOLDE will deliver high performance components also partly to the open-source community which will be used in industrial quality products. The excellent work carried out and the cooperation between partners during the meeting shows ISOLDE’s commitment to addressing real-world challenges and propelling Europe to the forefront of technological innovation.
Now, it is time to continue working together and drive positive impact across industries. As the project progresses, stay connected with ISOLDE through our website and social media channels!
The Industrial IoT has been an emerging market for several years now. As such, it has enabled manufacturing companies to increase production efficiency and to increase product quality. A major innovation driver is the usage of raw sensor and process data from production control systems and PLCs for downstream analytics tasks. With the convergence of Information Technology (IT) and Operational Technology (OT), many new use cases have appeared which allow to analyze fine-grained sensor data in real-time, to detect undesired situations and to apply these findings to improved process execution and optimized maintenance.
From a technical perspective, distributed edge-cloud architectures, often in combination with event-driven architectures, have emerged as the architectural paradigm of choice to realize such use cases. In these architectures, lightweight edge devices collect data directly from the shop floor (e.g., PLCs), pre-process data locally to reduce network traffic and to filter out irrelevant events and forward data to central systems (which might be at factory or cloud level) which provide the data analytics infrastructure. In addition, offloading of analytics tasks to edge nodes has recently become more popular due to increased processing power at the edge. This is especially useful for low-latency analytics applications.
Another shift in the past years was the uptake of open-source technologies in realizing such architectures. While the usage of open-source technologies is nothing new in the IT sector, with many market-dominant systems (e.g., in the Big Data world) being developed as open-source software, the manufacturing industry has started to adopt open-source technologies in their own stacks as well.
A popular open-source project in the Industrial IoT domain is Apache StreamPipes. StreamPipes is positioned as a self-service tool for flexible data analytics and realizes a development platform for industrial analytics applications. As an end-to-end toolbox, StreamPipes supports fast connectivity with a set of reusable adapters for popular industrial protocols (e.g., S7, Modbus, MQTT, OPC-UA), provides a pipeline tool to define alarming rules and notifications without programming and includes various tools for (visual) analytics. Many companies use Apache StreamPipes to gather and integrate Industrial IoT data and to run real-time analytics on continuous data streams in order to increase production efficiency, e.g., by implementing predictive maintenance applications.
Bytefabrik.AI is a technology startup from Karlsruhe, Germany with a focus on self-service manufacturing analytics applications for the Industrial IoT. The company follows an open core business model with Apache StreamPipes at its core.
Founded by the original creators of Apache StreamPipes, Bytefabrik.AI invests heavily in open-source development and contributes the latest software technologies for intelligent, real-time data analytics to the Apache StreamPipes project.
Within the ISOLDE project, Bytefabrik.AI aims to contribute substantial new features into Apache StreamPipes which will help to foster not only the RISC-V ecosystem in terms of application support in an evolving application area, but also help to develop future technological USPs for StreamPipes. We believe that RISC-V can become an important cornerstone of future Industrial IoT architectures - not only because of its open architecture. Several promises of RISC-V, e.g., energy-efficiency, ability to operate in low-power edge computing environments and low operating costs are highly relevant for distributed edge-cloud scenarios.
Planned development highlights of Bytefabrik.AI’s contributions within ISOLDE will be a lightweight edge client which will be able to stream data from source systems such as PLCs to a central Apache StreamPipes instance, an edge-cloud orchestrator to manage existing edge clients and an analytics runtime for time-series machine learning model execution. We will apply the technical outcomes to the Smart Home Demonstrator developed within ISOLDE.
We plan to make major parts of our technical achievements within ISOLDE part of Apache StreamPipes – this will ensure sustainable dissemination of project outcomes and will help to foster the RISC-V application ecosystem.
Links
Bytefabrik.AI – https://bytefabrik.ai
Apache StreamPipes – https://streampipes.apache.org
The automotive domain has witnessed a remarkable transformation in recent years, primarily driven by the pervasive integration of embedded systems. These specialized computer systems are the linchpin of modern vehicles, revolutionizing their performance, safety, and efficiency. In the context of motor control scenarios, the adoption of the RISC-V architecture stands out as a significant milestone. RISC-V, an open and extensible instruction set architecture (ISA), has gained prominence for its adaptability, modularity, and flexibility. It offers an innovative approach to addressing the intricate requirements of motor control in the automotive industry.
One significant extension of the RISC-V architecture for motor control is the incorporation of a vector accelerator unit (VAU). These VAUs provide the ability to execute parallel processing operations more efficiently, which is highly advantageous in motor control applications. By leveraging vector accelerator units, embedded systems can achieve improved computational performance and optimize energy consumption. The extension of RISC-V with VAUs empowers embedded systems to handle the intricate mathematics and algorithms required for motor control, contributing to improved performance and reduced energy consumption.
The aim to further optimize the RISC-V embedded architecture for the automotive domain is closely connected with the utilization of Power, Performance, and Area (PPA) analysis, as it turns out to be a crucial factor on the way to the deployment of an efficient solution. PPA analysis offers a comprehensive evaluation of the system's power efficiency, computational performance, and hardware area utilization. This analytical approach aids in fine-tuning the embedded system's architecture to strike an optimal balance between these critical parameters. By leveraging PPA analysis, engineers can design embedded systems that meet the stringent requirements of motor control while minimizing power consumption and overall hardware footprint.
The role of the ISOLDE project team from Brno University of Technology (BUT) from Czech Republic aims at the PPA optimization possibilities of a custom compute automotive instruction accelerator with vector processing capabilities, which represents an extension of RISC-V based target architecture developed in a close collaboration with the Codasip company (another Czech partner of the ISOLDE project). Obviously, the partnership between an academic institution and commercial company will be leveraged in that context.
The intended way of PPA optimization is two-fold. First, profiling of the processor setup (RISC-V core and accelerator unit) will be performed in Codasip Studio development tool with a special attention given to the Instruction Set Architecture (ISA) regarding:
Then, further optimization steps can be taken on so called Register Transfer Level (RTL) representation of the target embedded architecture. The capability of Codasip Studio to produce SystemVerilog representation of the whole hardware setup plays an important role here. Such kind of hardware description can be analyzed using Synopsys toolset, e.g. Design Compiler and RTL Architect, together with the help of ASIC technology libraries. Such an approach allows to refine the target architecture on a near-physical level with accurate power estimation, timing constraints and estimation of the floor area needed.
The advantages of this integrated approach accompanied by thorough PPA analysis and optimization steps are multifaceted. First, the adoption of RISC-V architecture with VAUs significantly enhances the processing power, enabling sophisticated control algorithms and real-time responses for motor control applications. Second, the extensibility and modularity of RISC-V make it adaptable to evolving motor control standards and requirements, facilitating future-proof designs. Lastly, PPA analysis-driven optimizations ensure that the embedded systems strike an optimal balance between performance, energy efficiency, and hardware utilization, thereby contributing to sustainable and reliable automotive solutions.
Links
Brno University of Technology (BUT) – https://www.fit.vutbr.cz
Development toolset by Codasip – https://codasip.com/products/codasip-studio/
Logic synthesis tools by Synopsys - https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test.html
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In a world where you have a casual conversation with your car and begin to wonder if it's already reading your mind, the automotive industry continues its intensive and ambitious collaboration with the RISC-V development community. Due to the high customizability, vehicle manufacturers can design, RISC-V is highly customizable, allowing manufacturers of vehicles to design processors tailored to their specific requirements. This adaptability is especially valuable when safety, performance, and power efficiency are critical properties. This new approach provides scalable end-to-end solutions, translating customers' needs into efficient and secure cross-domain platforms that allow for high re-use across carlines. It’s mandatory to all functional areas in the vehicle, from user experience in the cockpit, to an End-to-End vehicle network including the cloud, to automated driving and safety and motion functions.
As an integral component of the ISOLDE project, it’s a challenge for Continental Automotive to provide a high-performance computer architecture proposal versus actual existing VPU/GPU solutions. Currently incorporating the fully scalable “CV3” system-on-chip (SoC) family from semiconductor company Ambarella into our Advanced Driver Assistance Systems (ADAS). The powerful and energy efficient SoC solutions based on AI are tailored to assisted and automated driving applications and complement our portfolio. They offer more computing power, consume less energy, require less cooling and with this, save system costs.
Continental is collaborating with Infineon Technologies in the development of server-based vehicle architectures. The goal is an organized and efficient electrics/electronics (E/E) architecture with central high-performance computers (HPC) and a few, powerful Zone Control Units (ZCU) instead of up to a hundred or even more individual control units, as it was previously the case. Continental now uses Infineon’s AURIX TC4 microcontroller for its ZCU platform. Thanks to special storage technology in the AURIX TC4, the vehicle software is on standby. As soon as the vehicle is started, functions such as parking assistance, air conditioning, heating and suspension are ready within fractions of a second. With its platform approach, Continental is supporting the different requirements of the automobile manufacturers. By individually configuring the number of HPCs and ZCUs, how they interact and how they are arranged in the vehicle, automobile manufacturers can individually tailor their architecture to their needs.
Links:
https://www.eenewseurope.com/en/first-fully-coherent-risc-v-tensor-unit-...
Enabling the use of high-performance chips in safety-critical domains such as automotive, Space, and the like challenges the verification and validation of the system as a whole, and the deployment of appropriate safety measures to mitigate and manage errors. While there have been attempts to design high-performance chips where those issues, namely verification, validation and deployment of safety measures, are no more complex than in simpler designs by construction, they have not been matured and/or adopted due to multiple reasons such as limited performance, and lack of reuse of legacy IP. In this context, deploying features for verification, validation and safety measure realization while preserving legacy IP “as is” and performance unaffected becomes of paramount importance.
BSC, as part of its work in ISOLDE, is enhancing, integrating and maturing two components providing observability and controllability capabilities, as needed for verification, validation and safety measure realization. In particular, BSC contributes with the SafeSU statistics unit and the SafeTI traffic injector, which are being extended with additional capabilities to monitor components and inject traffic even in a different System-on-Chip (SoC), will be integrated as part of a Safety Island to interact with high-performance chips, and will undergo a strict validation process and include appropriate safety manuals. By providing out-of-the-band on-chip traffic monitoring and injection, misbehavior and resource abuse will be easier to be detected and reproduced, and safety measures deployed to avoid failures related to such misbehavior and resource abuse.
Both BSC components, the SafeSU and SafeTI, are specifically integrated in RISC-V SoCs and released with open source permissive licenses to ease their adoption and the development of European safety-relevant RISC-V SoCs with high-performance capabilities.
ISOLDE Project will have high performance RISC-V processing systems and platforms at least at TRL 7 for the vast majority of building blocks, demonstrated for key European application domains such as automotive, space and IoT with the expectation that two years after completion ISOLDE’s high performance components will be used in industrial quality products.
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